International organization research and development of stress-free polishing in TSV
2023-07-07 15:08:30
SHANGHAI, March 17, 2014 /PRNewswire/ -- Shengmei Semiconductor Equipment (Shanghai) Co., Ltd. and SEMATECH, an internationally renowned research and development organization, signed a contract with the well-known Huajin Semiconductor Packaging Pilot Technology R&D Center to jointly develop stress-free polishing. Application of TSV 3D and 2.5D Adapter Plate Metal Copper Layer Flattening Process.
With the rapid development of the semiconductor integrated circuit industry, in order to overcome the rapid development of design, development and production costs with the reduction of technology nodes, the concept of “post-Moore's Law†proposed by the packaging industry is different in the field of semiconductor packaging. The device replaces the original device technology node miniaturization with an integrated, three-dimensional TSV advanced package. However, the two major challenges faced by TSV's advanced packaging are the reliability of the manufacturing process and the cost of production.
“The beautiful stress-free polishing process can reduce the impact of wafer warpage caused by thick copper film on subsequent process reliability and greatly reduce the process cost of CMP.†Dr. Wang Hui, founder and CEO of Shengmei Semiconductor Equipment Co., Ltd. said "This contract between SMI and SEMATECH in the development of TSV 3D process is the first attempt of deep cooperation between Chinese semiconductor equipment companies and world-class R&D institutions. At the same time, through the development of TSV 2.5D adapter board with domestic Huajin Semiconductor. Cooperate to create a set of stress-free copper film flattening integration solutions with independent intellectual property rights, and promote the advanced technology in the field of domestic packaging to enter the international forefront."
In the advanced package TSV process, the cost of the CMP process exceeds 1/3 of the total cost. At the same time, the silicon wafer will warp due to the difference in thermal expansion coefficient (CTE) between the copper and the silicon substrate. This warpage will be amplified in the subsequent tempering process, which poses a huge challenge to the CMP process. In order to solve the above two problems, Shengmei developed SFP Stress-Free-Polish technology, which does not use traditional polishing liquid. There are no polishing pads and only recyclable electrochemical polishing fluids are used. Copper throwing costs are reduced by 87% compared to conventional CMP processes. The removal rate of stress-free polishing is less affected by the crystal phase structure of copper. The tempering process can be placed after the stress-free polishing process, which greatly reduces the warpage of the silicon wafer. By integrating with the CMP process, the CMP process is effectively solved. Technology and cost bottlenecks.
With the rapid development of the semiconductor integrated circuit industry, in order to overcome the rapid development of design, development and production costs with the reduction of technology nodes, the concept of “post-Moore's Law†proposed by the packaging industry is different in the field of semiconductor packaging. The device replaces the original device technology node miniaturization with an integrated, three-dimensional TSV advanced package. However, the two major challenges faced by TSV's advanced packaging are the reliability of the manufacturing process and the cost of production.
“The beautiful stress-free polishing process can reduce the impact of wafer warpage caused by thick copper film on subsequent process reliability and greatly reduce the process cost of CMP.†Dr. Wang Hui, founder and CEO of Shengmei Semiconductor Equipment Co., Ltd. said "This contract between SMI and SEMATECH in the development of TSV 3D process is the first attempt of deep cooperation between Chinese semiconductor equipment companies and world-class R&D institutions. At the same time, through the development of TSV 2.5D adapter board with domestic Huajin Semiconductor. Cooperate to create a set of stress-free copper film flattening integration solutions with independent intellectual property rights, and promote the advanced technology in the field of domestic packaging to enter the international forefront."
In the advanced package TSV process, the cost of the CMP process exceeds 1/3 of the total cost. At the same time, the silicon wafer will warp due to the difference in thermal expansion coefficient (CTE) between the copper and the silicon substrate. This warpage will be amplified in the subsequent tempering process, which poses a huge challenge to the CMP process. In order to solve the above two problems, Shengmei developed SFP Stress-Free-Polish technology, which does not use traditional polishing liquid. There are no polishing pads and only recyclable electrochemical polishing fluids are used. Copper throwing costs are reduced by 87% compared to conventional CMP processes. The removal rate of stress-free polishing is less affected by the crystal phase structure of copper. The tempering process can be placed after the stress-free polishing process, which greatly reduces the warpage of the silicon wafer. By integrating with the CMP process, the CMP process is effectively solved. Technology and cost bottlenecks.
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